1. Field of the Invention
The present invention relates to the detection of voltage levels on an integrated circuit such as a flash EEPROM. More particularly, this invention relates to a method and apparatus for detecting the supply voltage level where the power supply voltage may be less than the read potential required for sensing data in the memory of a flash EEPROM array.
2. Description of Related Art
As the market for personal computers has expanded, computer manufacturers have supplied the increasing demand with a continuous supply of new and better products. For instance, manufacturers continue to produce laptop computers that are smaller, lighter and more powerful. This has led to a need to reduce the power used by portable computers.
The integrated circuits that make up a large part of laptop computers have in the past been manufactured in order to work with a power supply voltage of about 5 volts, within a specified range of +/-10%. Of course other power supply voltages have been utilized. In order to reduce power consumption and extend battery life, much of the integrated circuitry used in personal computers is being redesigned to run at lower voltage levels. This reduces the power usage and allows more components to be placed closer to one another in the circuitry. For example, one low supply voltage which is emerging as a standard is specified to operate over a range of about 2.7 to 3.6 volts (hereinafter referred to as a 3 volt source). Other standards are being developed around even lower voltages. Thus, because of the many different combinations of components available in the present market, it is desirable to provide circuitry which is capable of functioning in systems providing either five volt, three volt, or five and three volt sources.
One computer component that is finding wide use in portable computers and that is affected by the level of the external voltage supply is the flash EEPROM array. Flash EEPROMs are a growing class of nonvolatile storage integrated circuits that may be used to provide a new form of long term random access storage which may replace electromechanical hard disk drives. These flash EEPROMs have the capability of electrically erasing, programming or reading a memory cell in the chip. The entire array can be simultaneously erased electrically. The flash EEPROM can also be randomly read or written.
The cells themselves use only a single transistor device per cell and are formed using so-called floating gate field effect transistors in which the data is stored in a cell by charging or discharging the floating gate. The floating gate is a conductive material, typically made of polysilicon, which is insulated from the channel of the transistor by a thin layer of oxide or other insulating material, and insulated from the control gate wordline of the transistor by a second layer of insulating material.
The act of charging the floating gate is termed the "program" step for a flash EEPROM. This is typically accomplished through a so-called hot electron injection by establishing a large positive voltage between the gate and source of the transistor, as much as 12 volts, and a positive voltage between the drain and source of the transistor, for instance, 6 volts. The act of discharging the floating gate is called the "erase" function for a flash EEPROM. This erasure function is typically carried out by a Fowler-Nordheim (F-N) tunneling mechanism between the floating gate and the source of the transistor (source erase) or between the floating gate and the substrate (channel erase). For instance, a source erase operation is induced by establishing a large positive voltage from the source to gate, while floating the drain of the respective memory cell. This positive voltage may be as much as 12 volts.
Given that flash EEPROMs can be programmed or erased by applying voltage to the device, systems incorporating flash EEPROMs often design capabilities to program and erase the flash EEPROMs. In order for a system to provide capabilities to program and erase the flash EEPROMs, the system has to provide not only a V.sub.CC voltage but also a V.sub.PP voltage. V.sub.CC is generally a 5 volt or 3 volt supply for controlling the logic in the read mode of the nonvolatile memory device. V.sub.PP is a 12 volt supply used in combination with V.sub.CC for controlling the programming and erasing modes of the nonvolatile memory device.
In order to provide the higher voltages necessary to program and erase flash EEPROM memory arrays, charge pump circuitry can be utilized. Charge pumps typically increase voltage available by pumping the voltage to a higher level. In the typical case, a five volt or three volt external source is pumped to twelve volts to provide voltages for programming and erasing. However, in a read operation, the word lines which supply a gate potential to memory cells are often designed to operate at a read potential of 4 volts or more. Thus, a low power supply voltage of 3 volts may be insufficient to directly supply an on chip voltage high enough to drive the word lines. This problem is dealt with by including charge pumps or other voltage supply boosters on the integrated circuits in order to supply the higher working voltages on chip.
Therefore, in such circuits, it is necessary to know the level of voltage available in order to know whether to pump the supply voltage to a higher value to read the array. U.S. Pat. No. 5,559,717, entitled "High Precision Voltage Detector Utilizing Flash EEPROM Memory Cells", invented by Tedrow et al., reveals a prior art apparatus that attempts to solve the above problem. This patent discloses the use of two flash memory cells (which consist of essentially identical floating gate FET devices) of a flash EEPROM, each with a different programmed switching voltage, in order to detect the level of the EEPROM's supply voltage. However, this detection scheme is subject to inaccuracy due to the inherent potential disturb problem of the flash memory cells. This could cause the detector voltage to be more susceptible to drift over time. Further, this apparatus requires a means for actively programming the flash cells to different voltages. This adds complexity and additional circuitry to the detector where space is at a premium, and also results in the consumption of additional testing time as the flash cells are programmed.
Accordingly, there is the need for an apparatus that is capable of detecting the voltage level of an external voltage supply to a computer component that improves upon and overcomes the problems and disadvantages of the prior art. In particular, there is the need for a device that can accurately, quickly, and reliably determine the level of a flash EEPROM supply voltage such that the flash EEPROM circuitry can be optimally designed. Further, the device needs to be free from the negative effects of floating gate FET time drift and the extra time and space requirements inherent in a voltage detector utilizing programmed switching of FET's.